About the Role

This permanent, full-time position joins the Optalysys analogue-design team in Bangalore. The role supports hybrid, onsite, or remote work and focuses on high-speed custom logic in advanced CMOS processes at or below 45 nm. The engineer will own circuit architecture, transistor-level design, verification, and correlation with measured silicon.

Responsibilities

• Architect serial and parallel adders, modular arithmetic units, shift registers, and other high-speed logic blocks.
• Implement and optimize domino and dynamic logic for speed, noise robustness, clocking, charge sharing, and timing margins.
• Close timing for deep pipelines and evaluate process, voltage, temperature, interconnect, and supply effects.
• Create simulation testbenches and run Spectre or APS analysis, including corner, Monte Carlo, and transient-noise work.
• Collaborate with layout engineers on parasitic-aware optimization and layout-dependent effects.
• Support design reviews, sign-off, silicon bring-up, validation, and simulation-to-silicon correlation.

Required Experience and Skills

• An MEng, MSc, or PhD in electronic engineering, electrical engineering, or a related field.
• Eight to ten or more years of analogue or custom IC-design experience.
• Successful domino or dynamic-logic tape-outs in CMOS nodes at or below 45 nm.
• Cadence Virtuoso, Spectre or APS, parasitic extraction, scripting, and silicon debug experience.

Preferred Experience

Helpful experience includes embedded memories, custom sense amplifiers, DLLs, PLLs, and very-high-frequency logic design.

How to Apply

Send a CV and cover letter to recruitment@optalysys.com. The source does not state a numeric salary or closing date.